Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis

The decrease of integrated circuit feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods, and model order reduction (MOR) methods have proven to be very effective in combating such high complexity. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the circuit under study as a function of design parameters such as geometrical and substrate features. Traditional MOR techniques perform order reduction only with respect to frequency, and therefore the computation of a new electromagnetic model and the corresponding reduced model are needed each time a design parameter is modified, reducing the CPU efficiency. Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We propose a novel PMOR technique applicable to PEEC analysis which is based on a parameterization process of matrices generated by the PEEC method and the projection subspace generated by a passivity-preserving MOR method. The proposed PMOR technique guarantees overall stability and passivity of parameterized reduced order models over a user-defined range of design parameter values. Pertinent numerical examples validate the proposed PMOR approach

Optimized Waveform Relaxation Solution of Electromagnetic and Circuit Problems

New algorithms are needed to solve electromagnetic problems using today\u27s widely available parallel processors. In this paper, we show that applying the optimized waveform relaxation approach to a partial element equivalent circuit will yield a powerful technique for solving electromagnetic problems with the potential for a large number of parallel processor nodes

Interpolation-based parameterized model order reduction of delayed systems

Three-dimensional electromagnetic methods are fundamental tools for the analysis and design of high-speed systems. These methods often generate large systems of equations, and model order reduction (MOR) methods are used to reduce such a high complexity. When the geometric dimensions become electrically large or signal waveform rise times decrease, time delays must be included in the modeling. Design space optimization and exploration are usually performed during a typical design process that consequently requires repeated simulations for different design parameter values. Efficient performing of these design activities calls for parameterized model order reduction (PMOR) methods, which are able to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as layout or substrate features. We propose a novel PMOR method for neutral delayed differential systems, which is based on an efficient and reliable combination of univariate model order reduction methods, a procedure to find scaling and frequency shifting coefficients and positive interpolation schemes. The proposed scaling and frequency shifting coefficients enhance and improve the modeling capability of standard positive interpolation schemes and allow accurate modeling of highly dynamic systems with a limited amount of initial univariate models in the design space. The proposed method is able to provide parameterized reduced order models passive by construction over the design space of interest. Pertinent numerical examples validate the proposed PMOR approach

Reduced order modeling of delayed PEEC circuits

We propose a novel model order reduction technique that is able to accurately reduce electrically large systems with delay elements, which can be described by means of neutral delayed differential equations. It is based on an adaptive multipoint expansion and model order reduction of equivalent first order systems. The neutral delayed differential formulation is preserved in the reduced model. Pertinent numerical results validate the proposed model order reduction approach

Multipoint model order reduction of delayed PEEC systems

We present a new model order reduction technique for electrically large systems with delay elements, which can be modeled by means of neutral delayed differential equations. An adaptive multipoint expansion and model order reduction of equivalent first order systems are combined in the new proposed method that preserves the neutral delayed differential formulation. An adaptive algorithm to select the expansion points is presented. The proposed model order reduction technique is validated by pertinent numerical results. A comparison with a previous model order reduction algorithm based on a single point expansion is performed to show the considerably improved modeling capability of the new proposed technique

A Spline-Based Partial Element Equivalent Circuit Method for Electrostatics

This contribution investigates the connection between Isogeometric Analysis (IgA) and the Partial Element Equivalent Circuit (PEEC) method for electrostatic problems. We demonstrate that using the spline-based geometry concepts from IgA allows for extracting circuit elements without an explicit meshing step. Moreover, the proposed IgA-PEEC method converges for complex geometries up to three times faster than the conventional PEEC approach and, in turn, it requires a significantly lower number of degrees of freedom to solve a problem with comparable accuracy. The resulting method is closely related to the isogeometric boundary element method. However, it uses lowest-order basis functions to allow for straightforward physical and circuit interpretations. The findings are validated by an analytical example with complex geometry, i.e., significant curvature, and by a realistic model of a surge arrester

The Partial Elements Equivalent Circuit Method: The State Of The Art

This year marks about half a century since the birth of the technique known as the partial element equivalent circuit modeling approach. This method was initially conceived to model the behavior of interconnect-type problems for computer-integrated circuits. An important industrial requirement was the computation of general inductances in integrated circuits and packages. Since then, the advances in methods and applications made it suitable for modeling a large class of electromagnetic problems, especially in the electromagnetic compatibility (EMC)/signal and power integrity (SI/PI) areas. The purpose of this article is to present an overview of all aspects of the method, from its beginning to the present day, with special attention to the developments that have made it suitable for EMC/SI/PI problems

Comparison of Via Equivalent Circuit Model Accuracy using Quasi-Static and Full-Wave Approaches

The EMC and signal integrity impact of printed circuit board (PCB) trace discontinuities, such as vias, where the signal is transitioned from one layer to another in the PCB stackup, have become significant recently with the use of very high speed signals in today\u27\u27s systems. If these discontinuities are ignored, significant distortion of the high speed signal can occur, and in many cases, cause data errors. A fast and accurate technique to include the effect of via discontinuities in the typical design process is needed to ensure this distortion is considered if significant. Therefore, a simple equivalent circuit for the via discontinuity is needed so that this equivalent circuit can be easily used in the normal signal integrity analysis tools. This paper demonstrates the effect on the equivalent circuit values as the distance between the signal via and the return-current via is increased. Also, the frequency range where a quasi-static based equivalent circuit is accurate or where a full-wave model is required is shown for the various distances between vias

System Level PDN Impedance Optimization Utilizing the Zeros of the Decoupling Capacitors

System-Level Power Distribution Network (PDN) Impedance Optimization Utilizing the Zeros of the Decoupling Capacitors (Decaps) is Discussed in This Paper. an Example of a Practical PDN Application is Proposed to Validate the Poles and Zeros Algorithm (P&Z) Presented. the System-Level PDN is with the Printed Circuit Board (PCB), Package (PKG), and Chip, as Well as the Low-Frequency Decaps on the PCB and the On-PKG Decoupling Capacitors. the PDN Optimization Results Are Compared with Those from the Genetic Algorithm (GA) to Show the Reasonableness and Validity of the P&Z Algorithm